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To demonstrate how
we can improve chip design productivity, we
are offering a 14-day free trial of our flagship product to
qualified prospects. Fill out a basic qualification form, and
our representative will contact you on the same business day.
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PRODUCT INFORMATION
Adeptix sells design-for-verification technology
that allows design teams
to radically improve productivity, dramatically reduce time and cost of the chip development process
while also improving product quality and achieving faster time to
market.
OVERVIEW
Adeptix offers the world's
most advanced design-for-verification entry, specification and
code generation technology.
Patent-pending Automatic
Specification Translator (ASTRA) Shuttle™ is the company’s
flagship product. Currently, the ASTRA Shuttle™ suite consists of
three independent tools. All tools are rooted in the library of
verification infrastructure components, which is now also
available for sale: Verification Pattern Library or ASTRA VPL™.
The ASTRA Shuttle™ suite addresses
three major early-stage design problems that cause revenue-affecting problems for chip
makers:
- Gap between specification and design on the one hand and verification on the other; hence the need for a
design-for-verification methodology and tools
- Barriers for adopting assertion-based coverage-driven design development; hence the need to streamline and facilitate the adoption process, and
- Lack of tools to document and verify design intent; hence the need to formalize specification patterns
ASTRA Shuttle™ includes the industry's first graphical assertion generation capability for all assertion languages, including
PSL, SystemVerilog Assertions and OVL.
Intuitive GUI and powerful specification and code generation capabilities allow chip designers to streamline, coordinate and synchronize specification, design and verification processes and to avoid specification errors, the most expensive errors in the chip design.
A wide variety of translation templates provide users with the most efficient way to generate code in any implementation or property specification language while meeting user-specific coding style requirements. Graphical formalization of design intent eliminates ambiguity and misinterpretation of specification documents, allowing for a better understanding of design
intent.
By integrating design together with verification data, ASTRA Shuttle™ represents the most practical, convenient and efficient design-for-verification solution.
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ASTRA Shuttle™
In today's design
process, it is a well known fact that approximately 60% of design
errors originate at the early stages of design. It is also well known
that up to 70%-80% percent of design team resources are spent on
verification. A simple calculation shows that about 40% of
project resources are spent on finding and correcting early-stage
design errors.
The most important
of the
three problems
mentioned earlier is the gap between design and
verification. Although the division
between design and verification is important, it also causes
certain problems. In a typical R&D organization today, designers and
chip architects are not involved in the verification process,
delegating
most of the verification work to a dedicated verification team.
Verification teams, in turn, concentrate on a black-box functional
verification, since they cannot follow all the details of the design
implementation. As a result, the riskiest parts of design
implementation are left unverified.
Architectural design
errors are the most expensive errors to fix. Fixing these errors requires a
backward re-iteration of multiple steps involving multiple design
teams and technologies. If a design error at the specification and
design stage slips into subsequent stages of design, it can cause
serious problems and even lead to a costly re-spin. Re-spins delay
product shipment by months, which can be fatal to the verification
team, the entire design team, or even the entire company.
Problem
1: Gap between
specification
and design on the one hand and verification on the other; hence the need
for a design-for-verification methodology and tools.
Solution:
The design-for-verification approach, when adopted as early as the
Specification stage, prevents costly architectural errors and decreases
the probability of chip respins. Responding to an increasing demand for a stable
design-for-verification methodology, ASTRA Shuttle™ provides the optimum solution for this
revenue-affecting problem by giving designers clarity and control
early in the design phase, when changes are easy to make.
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The second early-stage
chip design problem that causes chip makers to lose revenue has to do with
the exponential growth of verification complexity. This problem
cannot be solved without the adoption of assertion-based
verification. The adoption of assertion-based verification is
critical for the functional verification of large-scale chip
design, because it allows to overcome the exponential growth of
verification complexity. However, there are a number of barriers that
need to be removed in order to adopt assertion-based verification.
The main barrier for assertion-based verification is a lack of clear definition of
design-for-verification tasks, and when there are no clear
definitions, the job is left incomplete. Another barrier for assertion-based verification is the nature of assertion languages
itself. The nature of assertion languages is "intangible", which makes
it difficult to deal with for busy designers at the learning
stage. In addition, there are virtually no tools to support the
design-for-verification methodology. And, finally, in a typical design
organization, designers are less involved in assertions training
compared to verification engineers.
The adoption of assertion-based verification is
critical for the functional verification of large-scale chip
designs, because it allows to overcome the exponential growth of
verification complexity.
Problem
2:
Barriers for
adopting assertion-based coverage-driven design development; hence the
need to streamline and facilitate the adoption process.
Solution:
ASTRA Shuttle™ enables the industry’s first graphical assertion
and coverage generation capability for all assertion languages: PSL,
SystemVerilog Assertions and OVL.
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The third problem of the
early-stage design process Adeptix addresses is a lack of
specification tools. Every designer at a certain point goes to the
blackboard and draws diagrams using chalk. When this happens, it is a
good indication that a specific tool is needed.
In a typical chip design process, in order to graphically represent design
ideas and document their design intent, architects and designers have
to engage in a drawing process using
such consumer-oriented publishing editors as MS Word and Adobe FrameMaker.
This manual and labour-intensive drawing process is made even more
unproductive by a slow entry of design specifications and formatting
of design specification documents. In the end, the
design specification documents, written in human language using
consumer-oriented tools, become open for misinterpretations and
errors in the subsequent implementation. As a result, such a crucial
business success factor as quality of
the functional design is left heavily dependent upon designers' writing and
formatting skills, as opposed to their talent and professional
expertise.
Problem
3:
Lack of
tools to document and verify
design intent; hence the need to
formalize specification patterns.
Solution:
To reduce design cycle time, Adeptix examined the traditional design
methodology and identified areas in the design documentation process
where the manual entry of information could be automated, the drawing
tasks removed, and the skills of designers more efficiently
utilized.
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FEATURES AND BENEFITS
Patent-pending
Automatic Specification
Translator (ASTRA)
Shuttle™ consists of three independent tools: ASTRA
Wave™, ASTRA State™ and ASTRA Data™.
These tools are rooted in the
library of verification infrastructure components, which is also
available for sale: Verification Pattern Library or ASTRA VPL™.
ASTRA
Shuttle™
Features:
- Automatic generation of Assertions
code
- Automatic generation of Coverage
code
- Automatic generation of Constraint-Random Functional Models
- Automatic generation of Design code
with ASTRA State™
- Automatic generation of
Specification Documents
- Formal Validation of FSM Properties
with ASTRA State™
ASTRA Shuttle™
Benefits:
For
Designers:
-
Enables smooth and natural
transition to the assertion-based
verification methodology
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Significantly reduces assertion
and coverage coding work
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Ensures constant synchronization
between micro-architectural
specification and implementation
code
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Provides visual formalization
means exactly where designers
need it.
For Chip
Architects:
-
EE-specific graphical entry tools
replace general-purpose
graphical editors, reducing the
specification entry time
-
Concise and natural graphical
formalization removes ambiguity
and misinterpretations of
Specification Documents
-
Formal validation proves FSM properties during Specification
stage
-
Correlation between Specification
Documents and implementation
code is guaranteed for the entire
project cycle.
For Verification Engineers:
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Automatic generation of Constraint-Random Functional
Models
significantly reduces Testbench development time
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Automatic generation of
Verification Plan directly from Chip
Specification assures
tight correlation between verification and
design documents
and reduces the burden of document
synchronization work
throughout the project lifecycle
-
Clearly defines the interface
between design and verification
teams, allowing verification
engineers to concentrate more on
high-level functional
verification issues.
For Project as
a Whole:
-
Delivers key productivity
enhancements via tight integration
between specification,
implementation and verification code
-
Enforces design-for-verification
methodology as well as design
and verification coding styles
-
Enables incremental adoption of
assertion-based technologies
for both design and verification
teams
-
Facilitates project management
across distributed design and
verification teams by providing
a centralized specification
database
-
Clearly defines the scope of
verification responsibilities for
design and verification
teams
-
Seamlessly integrates with
existing design tools and
methodologies.
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DATASHEETS
Patent-pending
Automatic Specification
Translator (ASTRA)
Shuttle™ consists of three independent tools: ASTRA Wave™,
ASTRA State™ and ASTRA Data™. All three tools are rooted in and
based on the library of verification infrastructure components or
patterns: Verification Pattern Library or VPL.
Please note that basic
registration is required to download the datasheets. You will not be
required to complete this information the next time you download a
document from this website.
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ASTRA
Shuttle™
Datasheet
The
ASTRA Shuttle™ tool set
offers ability to integrate design together with verification
information and enables the industry's first graphical
assertion generation capability for all assertion languages,
including PSL, SystemVerilog Assertions and OVL. Intuitive GUI
and powerful specification and code generation capabilities
allow chip designers to streamline, coordinate and synchronize
specification, design and verification processes and to avoid
specification errors, the most expensive errors in the chip
design.
367KB
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WHITE PAPERS
Please note that basic registration is
required to download our white papers. You will not be
required to complete this information the next time you download a
document from this site.
Three Problems of the Early-Stage
Chip Design Process
This paper discusses three major factors that affect the
economic success of current design and verification
methodologies and explains how the design-for-verification
approach, adopted as early as the Specification stage, helps prevent costly architectural errors and even chip respins.
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DEMOS
To
get a quick introductory look at Adeptix tools, view a short online
demonstration of our products.
Our main product, ASTRA Shuttle™, consists of three independent tools:
ASTRA Wave™, ASTRA
State™ and ASTRA Data™.
All three tools are rooted in and based on the library of verification
infrastructure components or patterns: Verification Pattern Library or
ASTRA VPL™.
Note that basic registration is required to download the demos. The demonstration of each tool takes
approximately 6 minutes.
To give you a better understanding of our technology, we would be
happy to schedule an in-depth live demonstration of our tools via the
Internet or at your premises. This demonstration can be tailored to
reflect the needs of your particular project. To help us understand
your objectives, we request
that you fill out a qualification form and provide us with a basic
description of your project.
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EVALUATION
Adeptix is offering a
free 14-day product evaluation license to qualified prospects. Our
trials are designed for commercial entities with at least 5 designers
in one location. The evaluation license is for the
ASTRA Shuttle™ tools suite.
SUPPORT
Our technical staff is ready to
support your use of our tools and to ensure that you receive the
highest productivity from them. Our team works to ensure that
customers receive the latest product releases and responds quickly to
any inquiries.
Use our services from the start of
your project and enjoy faster adoption of new technology and methods
plus improved project productivity early in the design process.
Our support package includes support
and maintenance 8 hours per
day, five days per week. This service includes support incidents via
phone, email and fax.
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Adeptix Inc. is now a research partner of IBM. This partnership will
help promote IBM's advanced verification solutions in Canada,
whereby Adeptix will gain access to IBM's state-of-the-art
formal verification tools and
services. Adeptix welcomes the opportunity to begin
a research relationship with one of the world's most renowned
technology leaders.
More>>
If you would like to receive more information about our
technology, please fill out a short contact page.
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